Buses are one of key communication channel between function units and inside memory blocks of processors to deliver data or commands. Advancement, if the jobs are executed by multiprocessor systems, the bus management is very important and it is depended by the arbitration strategy. In this paper, we issued the methodology of bus traffic, fixed priority ambition, that based system-on-chip and to combine to two DLX processors both having 32-bit and to be emulated in ARM SoC (System-on-Chip) Designer simulation tools. For convenience control the traffic scheme among cores, we accomplished a fixed priority arbiter. Through the bus race experiment, we obviously obtained the follows result while the duty times are increasing, but the numbers of bus collusion are not obviously grown. The results are very valid while multi-cores designing.